1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the same, and more particularly, the present invention relates to a semiconductor device having improved properties and to a method of manufacturing the same in which a number of process steps is reduced by controlling ion implantation process parameters in a peripheral circuit region and a cell array region.
2. Description of the Related Art
Recently, as the use of computers in information media is expanding, rapid developments in semiconductor memory devices have also taken place. That is, highly integrated devices having improved reliability and response times have been developed, resulting in semiconductor memories with high operational speeds and large storage capacities.
Highly integrated semiconductor devices are obtained by precise electrical isolation of various elements such as transistors, diodes, resistors, and the like formed on a semiconductor substrate. Isolation parameters are adopted at an early stage of the manufacturing process and define the size of an active region and process margins of subsequent processes.
Generally, the degree of integration of semiconductor devices has exhibited a fourfold increase every three years, while the physical area of the devices has only increased 1.4 times over that same period. Thus, the pitch size between elements has been reduced. As the pitch size between elements continues to be reduced, it becomes difficult to manufacture a device having satisfactory dielectric and refresh characteristics. The process of isolating an appropriately sized portion within a limited cell array region is one of the most difficult tasks associated with achieving highly integrated semiconductor devices.
Currently, an isolation method utilizing poly spacer local oxidation is widely used for the manufacture of active patterns having small pitch sizes. However, the resulting profile becomes distorted due to the formation of a bird""s beak at the side portion of the field oxide. This results in deterioration of the refresh characteristic.
To improve upon drawbacks associated with this problem, an ammonia (NH3) plasma process is utilized to increase the effective channel length and to compensate for the thickness of the field oxides. In this method, the growth of the bird""s beak by an oxidation of the side portion of the field oxide can be restrained through nitrification of the surface portion of the field oxide by the ammonia plasma.
The nitrification reduces the oxidation of the side portion of the field oxides, thereby increasing their thicknesses. In particular, the thickness of the field oxides can be increased by about 200 xc3x85 using the ammonia plasma treatment and this increases the effective field length to about 150 xc3x85. As such, this method advantageously results in increased process margins. However, the manufacturing process as a whole becomes more complicated.
In another method of increasing isolation, a channel stopping ion implantation is implemented under the active region. The ion implantation is carried out by applying high energy to ions and injecting the ions to penetrate the surface of a solid to be injected. Through the ion implantation, the number of impure elements and the junction depth of the active region can be correctly controlled. In addition, since the processing temperature is low, a photoresist layer can be utilized as a protection layer and the concentration of the injected impurity is almost uniform from the surface of a wafer. Further, the lateral spread of the impurity with respect to the vertical plane of the wafer surface is even less than that obtained by thermal spread.
For the silicon wafer, trivalent boron(B), pentavalent phosphor(P), arsenic(As) and the like can be utilized as the impurities. Since these elements do not have gaseous phases at ambient temperature, gaseous molecules including these impurities are utilized. BF3, BCl3, and the like can be exemplified as the molecules including boron, PH3 can be utilized as the molecules including phosphor, and AsH3 can be utilized as the molecules including arsenic. The ion implanting process will be schematically explained for implanting boron ions by utilizing BF3 gas.
First, BF3 gas molecules are introduced into a gas room so that the molecules and thermal electrons emitted from a heated filament collide. At this time, the thermions are accelerated by applying a voltage difference of about 100V to increase an ionization degree of the BF3 gas molecules and a magnetic field is applied to increase the collision probability. From the collision of the emitted thermions and the BF3 molecules, dissociated ions such as 10B+, F230, 11BF+, 11B+, and the like are produced and desired, 11B+ ions are selected and accelerated by an appropriate magnetic field in a sorter. (The numbers preceding the letter B designate atomic weights of boron.)
After extracting the desired ions at the plasma state, a high energy is applied to accelerate the ions so that the ions impact the surface of the wafer, and the thus accelerated ions are injected into the wafer. At this time, the applied energy determines the junction depth. In order to control the concentration of the impurity, the amount of ions per unit area (atoms/cm2), that is, dose is controlled. The ion implanted depth is controlled by the acceleration energy (eV) of the injected ions.
One important defect in the ion implanting process is a damage imparted on the crystal lattice of a single crystal silicon wafer after the collision of the ions of high energy onto the wafer. To recover the damage and to activate the injected impurities, an annealing at about 900-1000xc2x0 C. is implemented after the completion of the ion implantation process. Further, drawbacks in applying a high voltage and an introduction of poisonous gases accompany the ion implantation process. Nevertheless, the ion implantation process is commonly utilized for the formation of a P-well and N-well, for the control of a threshold voltage, and for the formation of a source/drain region.
The ion implantation process is utilized to overcome the problems caused by different processing parameters for forming a cell array region and a peripheral circuit region. For example, U.S. Pat. No. 5,576,226 (issued to Hwang) discloses a method for controlling the thickness of a gate oxide layer by selectively injecting oxidation promoting ions or oxidation retarding ions into a cell array region and a peripheral circuit region. In addition, U.S. Pat. No. 5,780,310 (issued to Koyama) discloses a method for forming a cell array region on a recess having a first impurity concentration and a peripheral circuit region having a second impurity concentration so that the cell array region is formed from a lower portion than the peripheral circuit region.
Commonly, the channel stopping ion implantation is carried out after forming the N-well/P-well and Si3N4/SiO2 pattern. Through utilizing the Si3N4/SiO2 pattern, B+ ions are injected for the P-well and P+ ions are injected for the N-well. This channel stopping ion implantation also is referred to as a field ion implantation.
Practically, the field ion implantation is separately implemented for the cell array region and the peripheral circuit region by utilizing different masks even for the same conductive type MOS regions such as NMOS or PMOS regions. The two regions have different ion implanting parameters because the thickness of a field oxide at the cell array region is about 1500 xc3x85 and that of the peripheral circuit region is about 2000 xc3x85. Although the formation of the field oxides is carried out simultaneously for the two regions, the thicknesses of the field oxides at the two regions become different because the critical dimension at the cell array region is narrower than that at the peripheral circuit region.
Similarly, the field ion implantation processes at the NMOS cell array region and the NMOS peripheral circuit region are carried out by utilizing different photo masks. Accordingly, when a photoresist pattern is formed by utilizing a photo mask, all the ion implantation processes applicable to an exposed region, such as an ion implantation for the formation of a well, a field ion implantation, and an ion implantation for controlling a threshold voltage are continuously carried out. Then, another photoresist pattern is formed by utilizing another photo mask to continuously implement corresponding ion implantation processes for an exposed region.
Hereinafter, an ion implantation method for a device having an NMOS cell array region and a CMOS peripheral circuit region will be explained in detail.
FIGS. 1A to 1C illustrate a conventional ion implantation method for a device having an NMOS cell array region CN and a first and a second peripheral circuit regions PN-1 and PN-2 of a CMOS type.
Referring to FIG. 1A, a photoresist pattern 11 for shielding NMOS type cell array region CN and PMOS type second peripheral circuit region PN-2 and for exposing NMOS type first peripheral circuit region PN-1 is formed on a substrate 10. An ion implantation for the formation of a P-well, field ion implantation, and an ion implantation for controlling a threshold voltage for first peripheral circuit region PN-1 are continuously implemented.
Referring to FIG. 1B, a photoresist pattern 12 for shielding cell array region CN and first peripheral circuit region PN-1 and for exposing second peripheral circuit region PN-2 is formed. An ion implantation for the formation of an N-well, field ion implantation, and an ion implantation for controlling a threshold voltage for second peripheral circuit region PN-2 are continuously implemented.
Referring to FIG. 1C, a photoresist pattern 13 for shielding first and second peripheral circuit regions PN-1 and PN-2 and for exposing cell array region CN is formed. An ion implantation for a formation of a P-well, field ion implantation, and an ion implantation for controlling a threshold voltage for cell array region CN are continuously implemented.
As shown in the figures, the ion implantation processes for first peripheral circuit region PN-1 and cell array region CN are separately implemented even though they are the same NMOS type. The kind of ions, applied energy, and dose for each ion implantation process will be exemplified for first peripheral circuit region PN-1 and cell array region CN. The explanation on second peripheral circuit region PN-2 of the PMOS type will be omitted.
For the first peripheral circuit region PN-1, the ion implanting parameters for formation of the P-well are 11B+, 500 KeV, 1.0xc3x971013; the ion implanting parameters for formation of the field ion implantation are 11B+, 120 KeV, 9.0xc3x971012; and the ion implanting parameters for control of the threshold voltage are 11B+, 50 KeV, 1.0xc3x971012. Likewise, for the cell array region CN, the ion implanting parameters for the formation of the P-well is 11B+, 500 KeV, 1.0xc3x971013; the ion implanting parameters for formation of the field ion implantation are 11B+, 100 KeV, 7.5xc3x971012; and the ion implanting parameters for control of the threshold voltage are 49BF2+, 50 KeV, 6.2xc3x971012. (The numeral 11 of 11B+ indicates the atomic weight of boron and the numeral 49 of 49BF2+ indicates the molecular weight of BF2+.) The differences in the field ion implanting parameters are attributed to the difference in thicknesses of the field oxides at the two regions. That is, since the field oxide at the peripheral circuit region is thicker than that at the, cell array region, the parameters applied for the peripheral region is stronger.
In conclusion, even though the parameters for the formation of the wells are the same for the two regions, the ion implantation processes are separately implemented because the parameters for the subsequent ion implantation processes are different. In the above-described conventional method, a large number of process steps are required for the manufacture of the semiconductor devices. Thus, the manufacturing process is complicated and the productivity (production rate) of the device is very low.
Accordingly, it is an object of the present invention to provide an advantageous method for manufacturing a semiconductor device which has reduced processing steps and an improved productivity.
It is a further object in the present invention to provide a semiconductor device having improved properties which can be manufactured by such an advantageous method.
According to one aspect of the present invention, a semiconductor device is provided which includes a cell array region and a peripheral circuit region. The cell array region and the peripheral circuit region have corresponding ion implanted regions of a same object and a same conductive MOS type. Further, the cell array region includes a first ion implanted region which has a same depth and dose as an ion implanted region formed on the peripheral circuit region, and a second ion implanted compensation region. The ion implanted region can be formed by field ion implantation process or ion implantation process for controlling a threshold voltage. The second ion implanted compensation region can be formed above the first ion implanted region from a bottom portion of a substrate or a depth of the second ion implanted compensation region can be the same as a depth of the first ion implanted region.
According to another aspect of the present invention, a method of manufacturing a semiconductor device is provided which includes forming a first mask which exposes a cell array region and a peripheral circuit region of a semiconductor substrate. The cell array region and the peripheral circuit region having a same conductive MOS type. Then, a preceding ion implantation process is implemented in both the cell array region and the peripheral circuit region utilizing the first mask. The preceding ion implantation process has ion implantation parameters corresponding to first implantation design specifications of one of the cell array region and the peripheral circuit region. Then, a second mask is formed which shields the one of the cell array region and the peripheral circuit region and which exposes the other of the cell array region and the peripheral circuit region. Then, a subsequent ion implantation process is implemented in the other of the cell array region and the peripheral circuit region utilizing the second mask. The subsequent ion implantation process has ion implantation parameters which compensate for a difference between the ion implantation parameters of the preceding implantation process and second implantation design specifications of the other of the cell array region and the peripheral circuit region.
According to still another aspect of the present invention, a method of manufacturing a semiconductor device is provided with includes forming a first mask which exposes a cell array region and a peripheral circuit region of a semiconductor substrate, the cell array region and the peripheral circuit region each being of a same conductive MOS type. Then, a first ion implantation for forming a well, a second ion ion implantation for forming a field, and a third ion implantation for controlling a threshold voltage are conducted in both the cell array region and the peripheral circuit region utilizing the first mask. Ion implantation parameters of the first, second and third ion implantations correspond to implantation design specifications of the peripheral circuit region and include an implantation angle of about 7xc2x0 from normal. Then, a second mask is formed which shields the peripheral circuit region and which exposes the cell array region. Then, a fourth ion implantation for forming a field and a fifth ion implantation for controlling a threshold voltage are conducted in the cell array region utilizing the second mask. Ion implantation parameters of the fourth and fifth ion implantations compensate for a difference between the ion implantation parameters of the second and third implantation processes and implantation design specifications of the cell array region and include an implantation angle of about 0xc2x0 from normal.